Parameter tolerant pll synthesizer

Details Parameter tolerant pll synthesizer Parameter tolerant pll synthesizer

H - Electricity

03

J

H03J 5/00 (2006.01) H03J 7/06 (2006.01) H03L 7/089 (2006.01) H03L 7/093 (2006.01) H03L 7/18 (2006.01)

Patent

CA 2071524

In a PLL synthesizer, the tolerance to gain and component variations is greatly reduced when the gain of the loop is increased above that which the loop was initially designed for and if the third order loop symmetric ratio is reduced to a value within the range of 2.0 to 2.5. Higher order loops based on the third order symmetric ratio range have correspondingly lower transmission pole frequency to open loop unity gain frequency ratios.

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