Parity detection system for wide bus circuitry

Details Parity detection system for wide bus circuitry Parity detection system for wide bus circuitry

G - Physics

06

F

340/75

G06F 11/10 (2006.01)

Patent

CA 1267460

ABSTRACT OF THE DISCLOSURE A parity checking system for establishing integrity of data transfer on a wide bus. Each set of "4" bus lines of a multiple line bus is passed from a driver chip to a corresponding receiver chip. An added parity driver chip senses each corresponding bit line of each driver chip to develop a set of four parity signals for comparison with corresponding parity signals from each corresponding bit line of each one of a set of receiver chips. Any discrepancy will generate a parity error signal.

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