Partial isolation of power rails for output buffer circuits

Details Partial isolation of power rails for output buffer circuits Partial isolation of power rails for output buffer circuits

H - Electricity

03

K

H03K 19/0175 (2006.01) H03K 17/16 (2006.01) H03K 19/00 (2006.01) H03K 19/003 (2006.01)

Patent

CA 2084600

Attorney Docket No. NS18695 PARTIAL ISOLATION OF POWER RAILS FOR OUTPUT BUFFER CIRCUITS Abstract An output buffer circuit (10) delivers output signals of high and low potential levels at an output (VOUT) in response to data signals at an input (VIN). The output buffer circuit comprises an input stage (12) coupled between a relatively quiet power supply rail (VCCQ) and a relatively quiet power ground rail (GNDQ), and an output stage (14) coupled between a relatively noisy power supply rail (VCCN) and a relatively noisy power ground rail (GNDN). A first coupling resistor (R5) is coupled between the relatively quiet and noisy supply rails (VCCQ, VCCN) for reducing cc droop in the relatively noisy supply rail (VCCH) which in turn reduces output step in voltage during transition from low to high potential level (LH) at the output (VOUT). The first coupling resistor (R5) has a low resistance value selected for partially coupling the supply rails while maintaining partial isolation for maintaining input dynamic threshold levels for other non-switching quiet output buffer circuits coupled to a common bus. A second coupling resistor (R5A) is coupled between the relatively quiet and noisy ground rails (GNDQ,GNDN). The second coupling resistor (R5A) has a low resistance value selected for partially coupling said ground rails while maintaining partial isolation also protecting input dynamic threshold levels of quiet outputs. The first coupling resistor (R5) is coupled between supply rail bond pads (20,22), while the second coupling resistor (R5A) is coupled between ground rail bond pads (30,32). The power rail bond pads (20,22) (30,32) are coupled respectively to split leads (24,25) (34,35) of a split lead leadframe merging respectively to a common VCC pin (28) and a common GND pin (38).

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