H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/134
H01L 21/203 (2006.01)
Patent
CA 1044378
PARTIAL PLANARIZATION OF ELECTRICALLY INSULATIVE FILMS BY RESPUTTERING Abstract of Disclosure A method of partially planarizing an electrically insulative layer over an integrated circuit substrate which has a raised line metallization pattern having narrower lines and wider lines. The insulative layer has narrower and wider elevations corresponding to the underlying lines. Resputtering of said insulative layer is conducted for an amount of time sufficient to planarize the narrower elevations in the layer but insufficient to so planarize its wider elevations. This method is useful in planarizing insulative layer elevations through which via holes are to be formed, particularly via holes which are wider than the under- lying metallizing lines which they contact. Such a planarization method in via hole formation avoids the tunneling effects which would otherwise result from the over-chemical etching necessary to form the via holes.
298325
Lechaton John S.
Richard Leo P.
Smith Daryl C.
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