Partially aligned multi-layered circuitry

Details Partially aligned multi-layered circuitry Partially aligned multi-layered circuitry

H - Electricity

01

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356/30

H01L 23/52 (2006.01) H01L 23/538 (2006.01) H05K 1/00 (2006.01) H05K 3/32 (2006.01) H05K 1/11 (2006.01) H05K 3/00 (2006.01) H05K 3/30 (2006.01) H05K 3/40 (2006.01) H05K 3/46 (2006.01)

Patent

CA 1223085

-30- ABSTRACT Electrical circuitry 32 is comprised of a plurality of layers 30, 100, each layer 30, 100 including one or more electrical pathways 36, 38, each layer 30, 100 also including insulation 34 for insulating at least part of one layer 30 from another layer 100. The pathways 36, 38 comprise repeating patterns 40, 42. Each pathway 36, 38 of each layer 30, 100 can communicate with the pathways 36, 38 of the next adjacent layers 30, 100. Some portions of the patterns 40, 42 which comprise the pathways 36, 38 of each layer 30, 100 can be at least partially aligned with some portion of the patterns 40, 42 of pathways 36, 38 of the other layers 30, 100. Other portions of the pathways 36, 38 of the layers 30, 100 remain unaligned. A pulse laser 134 can be used to sever unaligned portions of the pathways 36, 38 as appropriate to create the desired electrical circuitry 32. Components can be secured to the electrical circuitry as required. Further, such circuitry can be used in the construction of the final metallization layers of chips such as gate arrays.

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