Partially depleted soi mosfet with self-aligned body tie

Details Partially depleted soi mosfet with self-aligned body tie Partially depleted soi mosfet with self-aligned body tie

H - Electricity

01

L

H01L 27/12 (2006.01) H01L 21/84 (2006.01) H01L 29/786 (2006.01)

Patent

CA 2487729

A silicon-on-insulator (SOI) device structure 100 formed using a self-aligned body tie (SABT) process. The SABT process connects the silicon body of a partially depleted (PD) structure to a bias terminal. In addition, the SABT process creates a self-aligned area of silicon around the edge of the active areas, as defined by the standard transistor active area mask, providing an area efficient device layout. By reducing the overall gate area, the speed and yield of the device may be increased. In addition, the process flow minimizes the sensitivity of critical device parameters due to misalignment and critical dimension control. The SABT process also suppresses the parasitic gate capacitance created with standard body tie techniques.

Une structure de dispositif silicium sur isolant (SOI) (100) est obtenue par un procédé de raccordement de corps autoaligné (SABT). Le procédé SABT permet de connecter le corps de silicium d'une structure partiellement appauvrie (PD) pour polariser une borne. Par ailleurs, le procédé SABT crée une zone de silicium autoaligné autour du bord des zones actives, comme celle formée par le masque de diffusion de transistor standard, ce qui permet d'obtenir une topologie de dispositif à rendement surfacique. De plus, la réduction de la zone de grille globale permet d'augmenter la vitesse et le rendement du dispositif. Le déroulement du processus réduit au minimum la sensibilité des paramètres de dispositif critiques en raison du désalignement et du contrôle de dimension critique. Le procédé SABT supprime également la capacitance de grille parasite engendrée par les techniques de raccordement de corps classiques.

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