Peripheral component interconnect bus memory address decoding

Details Peripheral component interconnect bus memory address decoding Peripheral component interconnect bus memory address decoding

G - Physics

06

F

G06F 13/16 (2006.01) G06F 13/10 (2006.01) G06F 13/42 (2006.01)

Patent

CA 2371509

A peripheral component interconnect (PCI) bus memory addressing system comprising a memory address decoder and disconnection means connected to a PCI bus, the disconnection means being arranged to disconnect one or more signals of the PCI bus from a first PCI device, wherein the memory address decoder is arranged to selectively activate the disconnection means such that an address which falls within an address range identified in a base address register of the first PCI device and a base address register of a second PCI device will be received by the second PCI device but not by the first PCI device.

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