Phase comparator insensitive to clock asymmetry

Details Phase comparator insensitive to clock asymmetry Phase comparator insensitive to clock asymmetry

H - Electricity

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H04L 7/02 (2006.01) G01R 25/00 (2006.01) G01R 25/08 (2006.01) H03K 17/66 (2006.01) H03L 7/08 (2006.01) H03L 7/089 (2006.01)

Patent

CA 1280177

PHASE COMPARATOR INSENSITIVE TO CLOCK ASYMMETRY ABSTRACT OF THE DISCLOSURE A phase comparator generates a reference pulse equal in duration to one bit cell, and a variable pulse having a duration representative of the duration and time displacement of the leading edge of a data pulse from the center of the bit cell. The phase comparator includes two D-type flip-flops arranged so that the variable pulse is initiated by the leading edge of the data pulse in the one bit cell, the reference pulse is initiated by the edge of the clock pulse at the end of the one bit cell, and both pulses are terminated by the edge of the clock pulse at the end of the next bit cell. Hence, only clock edges at the bounds of the bit cell affect the pulse durations and the apparatus is insensitive to clock asymmetry. The charge pump associated with the comparator provides a pump down signal amplitude equal to 3/2 the pump up signal amplitude to correct the relationship that the variable pulse (which generates the pump up signal) is 3/2 the duration of the reference pulse (which generates the pump down signal) where the data pulse edge is nominally in the center of the bit cell.

560294

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