Phase corrected clock signal recovery circuit

H - Electricity – 04 – L

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328/87

H04L 7/02 (2006.01) H04L 7/033 (2006.01) H04L 25/49 (2006.01)

Patent

CA 1185332

Abstract of the Disclosure A phase corrected clock signal recovery circuit for multilevel digital signals includes a transition marker generator for generating a narrow width pulse each time a received multilevel digital signal crosses one of the threshold levels between the adjacent logic levels of multilevel signal. Picket fence-like pulse trains are thus formed, the pulses (transition markers) of which correspond to the threshold crossings of the received digital signal, The pulse trains are interspersed with spaces or eye intervals which correspond to the absence of any threshold crossings. Each eye interval addition- ally corresponds to the time during which each respec- tive bit of digital signal information is transmitted. The rate of occurrence of the pulse trains is substan- tially equal to the clock frequency of the received digital signal. A phase error correction circuit is operatively coupled to the output of the transition marker generator and to an electronically tuned bandpass filter capable of adjusting the phase of the pulse trains. More specifically, the phase error detection circuit includes an up/down counter and adjusts the phase of the clock signal recovered from the pulse trains such that the number of transition markers generated during the high portion of the clock signal equals the number of transition markers generated during the low portion of the clock signal. Thus, selected transitory edges of the pulses of the recovered clock signal are centered at the middles of the respective eye intervals, that is, at the points in time when each respective bit of multilevel digital signal information occurs. This phase corrected recovered clock signal is conveniently applied to appro- priate sampling circuitry to enable sampling of the multilevel digital signal at optimum times, that is, at the center of the eye intervals.

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