G - Physics
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R
G01R 25/00 (2006.01) H03L 7/091 (2006.01) H04L 7/033 (2006.01) H04L 25/497 (2006.01) G11B 20/10 (2006.01)
Patent
CA 2258655
A phase detector determines an error value dependent on the relative phase between a local oscillator signal, used as the system clock, and an input signal received over a PR (a, b, a) channel. The phase error value is used to control a phase locked loop (Figure 1, not shown). The received signal is sampled at regular intervals dependent on the local oscillator signal. A threshold dicer 22 selects an ideal sample value for a sampling point by comparing the sampled value to three thresholds provided on respective ones of slicer threshold inputs 23, 24 and 25. A subtracter 27 determines a difference value corresponding to a difference between the ideal sample value and the actual sample value for that sampling point. A delay register 28 and a subtractor 29 operate to determine the sense of change to the current ideal sample value from an ideal sample value for a preceding sample point. An output of the subtractor is applied to the switching input of a switch, which thereby provides as an output signal either the difference value or the inverse of the difference value, provided by an inverter 32, dependent on the detected sense of change.
Popplewell Andrew
Williams Stephen
Fetherstonhaugh & Co.
Lsi Logic Corporation
Mitel Semiconductor Limited
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