Phase locked loop decoder

Details Phase locked loop decoder Phase locked loop decoder

H - Electricity

03

L

328/87, 352/19.5

H03L 7/00 (2006.01) G11B 20/14 (2006.01) H04L 25/49 (2006.01)

Patent

CA 1063719

ABSTRACT OF THE DISCLOSURE A phase locked loop decoder for decoding digitally encoded data is disclosed in which each incoming data bit is synchronized to a clock frequency and a derived signal representative of the data cell width is varied in accordance with a derived phase error signal to compensate for bit shift and for data cell width variation which may be present in the incoming data. The phase error signal is pulsed waveform having a leading edge synchronized with the occurrence of each data transition and a pulse width representative of the phase error of the data with respect to the clock. The decoder will detect and decode data transitions having bit shifts of up to plus or minus fifty percent of the bit cell period.

248029

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