Phase-locked loop having a slight phase offset error

Details Phase-locked loop having a slight phase offset error Phase-locked loop having a slight phase offset error

H - Electricity

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H03L 7/00 (2006.01) H03D 13/00 (2006.01) H03L 7/085 (2006.01) H04B 3/36 (2006.01)

Patent

CA 1047126

ABSTRACT In a phase-locked loop the phase offset error arising because of imperfections in the balance of the phase comparator using a first pair of balanced diode peak detectors jointly pro- ducing a detection voltage is reduced by also using a second pair of balanced diode peak detectors responsive to the reference signal and the reference signal in opposite phase for jointly producing a compensation voltage, and an output circuit for dif- ferentially combining the detection and compensation voltages so as to produce a phase comparator output voltage substantially free from offset voltage. The quasi-static phase error of the loop may then be reduced to very low values so that the loop is particularly suited for recovering the clock frequency from synchronous pulse signals having clock frequencies of several hundred MHz.

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