Phase locked loop including non-integer multiple frequency...

Details Phase locked loop including non-integer multiple frequency... Phase locked loop including non-integer multiple frequency...

H - Electricity

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H04L 7/02 (2006.01) H03B 19/00 (2006.01) H03L 7/099 (2006.01) H03L 7/18 (2006.01) H03L 7/197 (2006.01) H04J 3/07 (2006.01)

Patent

CA 2036135

A digital phase locked loop is employed to realize an output clock signal from a reference signal having a frequency which is not an integer multiple of the output clock signal frequency. This is realized by employing a programmable divider for dividing the reference signal which is dynamically controlled by a controllably variable base divisor. The base divisor control is responsive to the reference signal and to a phase error signal. The base divisor is generated to obtain a desired fractional division of the reference signal frequency and in a manner tominimize the amplitude of any resulting "high" frequency jitter in the output clock signal from the loop. (FIG. 1)

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