Phase-locked loop (pll) circuit for selectively correcting...

Details Phase-locked loop (pll) circuit for selectively correcting... Phase-locked loop (pll) circuit for selectively correcting...

H - Electricity

03

D

H03D 3/24 (2006.01) G06F 1/10 (2006.01) H03D 3/02 (2006.01) H03L 7/06 (2006.01) H04L 25/49 (2006.01)

Patent

CA 2468269

A phase-locked loop (PLL) circuit (100) includes multiple selectable feedback and a mode selector (160) for selecting different feedback paths in different operating modes. The PLL circuit (100) corrects for clock skew or produce a desired degree of clock skew between input and output clock signals in different operating modes.

L'invention concerne un circuit (100) en boucle à phase asservie (PLL) qui comporte une rétroaction multiple sélectionnable et un sélecteur de mode (160) qui permet de choisir différents chemins de rétroaction en différents modes. Le circuit (100) PLL corrige le désalignement d'horloge ou produit un niveau de désalignement d'horloge voulu entre des signaux d'entrée et de sortie en différents modes de fonctionnement.

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