Phase locked loop stabilization circuitry

Details Phase locked loop stabilization circuitry Phase locked loop stabilization circuitry

H - Electricity

04

N

331/34, 350/68

H04N 9/12 (2006.01) H03L 7/099 (2006.01) H03L 7/22 (2006.01) H04N 9/45 (2006.01)

Patent

CA 1305786

RCA 82,969 Abstract of the Disclosure A digital television receiver includes a first phase locked loop which develops a sampling clock signal that is locked to the horizontal line synchronizing signal components of a composite video signal. A second digital phase locked loop is clocked by the sampling clock signal and develops a digital signal that is phase locked to the color burst signal. This digital signal is used as a regenerated color subcarrier signal to synchronously demodulate the chrominance components of the composite video signals into I and Q color difference signals. To compensate for frequency instability in the regenerated subcarrier signal caused by frequency instabilities in the line-locked clock signal, a third digital phase locked loop develops an output signal which is phase locked to a reference signal generated by a crystal controlled oscillator. Control signals from -the third phase locked loop are applied to the second phase locked loop to substantially compensate for frequency instabillties in the regenerated subcarrier signal that are induced by the clock signals.

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