Phase locked loop system

Details Phase locked loop system Phase locked loop system

H - Electricity

03

L

331/35, 350/70

H03L 7/08 (2006.01) H03L 7/087 (2006.01) H04N 9/45 (2006.01) H04N 9/455 (2006.01)

Patent

CA 1257381

Abstract of the Disclosure A digital television receiver, having a line-locked clock, includes a partly digital, partly analog phase locked loop. This phase locked loop regenerates two quadrature phase related subcarrier signals that are used to synchronously demodulate the chrominance signal components of the composite video signals into two color information signals. The phase locked loop includes an analog voltage controlled oscillator which generates a signal that is independent of any frequency instability in the line locked clock signal. An analog-to-digital converter digitizes this signal to provide one of the subcarrier signals. This subcarrier signal is applied to a read-only memory to generate the second subcarrier signal. The two color information signals are obtained by multiplying the chrominance signals by the first and second subcarrier signals. A phase comparator determines the phase of the vector sum of the two color information signals and compares this against a desired phase value to generate a phase difference signal. The phase difference signal is filtered and applied to a digital-to-analog converter which provides the frequency control signal for the analog voltage controlled oscillator. In a second embodiment of the invention, a tracking filter is inserted at the output port of the analog-to-digital converter to allow the quantization resolution of the analog-to-digital to be reduced without affecting the performance of the phase locked loop.

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