Phase-locked loop with d.c. modulation capability

Details Phase-locked loop with d.c. modulation capability Phase-locked loop with d.c. modulation capability

H - Electricity

03

K

331/35, 331/64

H03K 3/72 (2006.01) H03C 3/09 (2006.01) H03K 7/06 (2006.01) H04L 27/12 (2006.01)

Patent

CA 1194156

Abstract A circuit for changing the frequency of a pulse train in response to a change in the average value of an applied digital signal applies the signal to be changed to a pulse subtractor. Application of a predetermined number of digital data signals of one sign causes the periodic subtraction of the pulse at the subtractor, thus reducing the average freguency at the output from the pulse subtractor. The signal at the output from the subtractor is applied to a pulse adder which adds a pulse to the subtracted pulse trained in response to a predetermined number of data pulses of the opposite sign. The output pulse train is thus varied in frequency in response to variation in the average value of the digital data input. The order of addition and subtraction may be reversed, and one of the functions can be performed in the feedback loop of a frequency synthesizer.

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