H - Electricity – 04 – J
Patent
H - Electricity
04
J
H04J 3/02 (2006.01) H03L 7/107 (2006.01) H04J 3/06 (2006.01)
Patent
CA 2095350
A phase-locking circuit for jitter reduction in a digital multiplex system includes a feed-back operational amplifier having two inputs. Two anti-parallel coupled diodes are arranged at one input of the operational amplifier for achieving automatic gain control. The other input of the operational amplifier is connected to a reference voltage. The operational amplifier is of the FET or CMOS type, having high-ohmic amplifier inputs.
Circuit de verrouillage de phase permettant de réduire la gigue dans un système multiplex numérique. Comprend un amplificateur opérationnel à réaction, à deux entrées. Deux diodes sont montées tête-bêche à une entrée de l'amplificateur opérationnel aux fins de la commande de gain automatique. L'autre entrée de l'amplificateur opérationnel est connectée à une source de tension de référence. L'amplificateur opérationnel est de type FET ou CMOS, à entrées à haute valeur ohmique.
Marks & Clerk
Telefonaktiebolaget Lm Ericsson
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