Phase-regulating circuits

Details Phase-regulating circuits Phase-regulating circuits

H - Electricity

04

L

328/87

H04L 7/02 (2006.01) H04L 7/033 (2006.01)

Patent

CA 1273413

9 ABSTRACT: Phase-Regulating Circuits: Phase-regulating circuits (PLL) which convert a slot clock signal at an input (1) into an error-free clock signal with a low jitter at an output (8), comprising a phase discriminator (3), two identical frequency dividers (2,9) and a regulating oscillator (7). The latter contains a crystal oscillator (15) which supplies an auxiliary frequency (FH), and an adding counter (11) which generates a further signal with a frequency (FX). One control input of the adding counter (11) is connected for this purpose to the output (6) of the phase discriminator (3), whilst a second is connected to the output of the crystal oscillator (15). The auxiliary frequency (FH) and the further frequency (FX) are each connected to an input of an EXCLUSIVE-OR gate (13) by which they are added by regular polarity reversal. From this added frequency (FH + FX) a frequency divider (12) obtains the frequency (FA) of the clock signal. A plurality of phase-regulating circuits (PLL) can operate using a common crystal oscillator (15). This is of particular interest for digital signal multiplex devices.

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