Physical partitioning of logically continuous bus

Details Physical partitioning of logically continuous bus Physical partitioning of logically continuous bus

G - Physics

06

F

G06F 13/16 (2006.01) G06F 13/40 (2006.01)

Patent

CA 2092631

Arrangements are disclosed for physically partitioning a bus having a well defined architecture as a physical entity, wherein the partitioning is logically transparent to a computer and devices which communicate through the bus and serves to avoid problems potentially arising because of the scope of actions permitted by the architecture. A typical bus architecture to which present arrangements have relevance is that associated with SCSI (Small Computer System Interface) buses. The potential problems allowed to occur architecturally involve: (a) exposures of data security/integrity; (b) excessive signal degradation due to use of signal rates which although allowed by the architecture are inappropriate for a particular bus loading environment also allowed by the architecture; (c) restrictions preventing parallel transfer of data between the computer and multiple storage devices; (d) restrictions unduly limiting the number of devices attachable to one logical bus path (one input-output channel of the computer). The disclosed arrangement partitions the bus into two or more physical entities which to the computer appears as one logical entity.

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