Pipeline arithmetic unit

Details Pipeline arithmetic unit Pipeline arithmetic unit

G - Physics

06

F

354/204

G06F 7/50 (2006.01) G06F 7/52 (2006.01)

Patent

CA 1270569

PIPELINE ARITHMETIC UNIT Abstract A fast pipeline adder comprising a plurality of registered adder rows. In one embodiment, additions in the pipeline are realized in reclocked half adders. In another embodiment, modified adders are employed which accept two carry inputs and develop two carry outputs. The resulting number of individual cells is reduced to approximately half of those in the prior embodiment. In still another embodiment, switch means are included in each cell to delete the reclocking and in still another embodiment, the adders in the diagonal of the pipeline adder arc provided with additional inputs to permit use of the pipeline adder in recursive addition applications. In still another embodiment, tile cells are permitted to output the inverse of the intended signal, reducing thereby the physical realization of the cells and increasing the speed of the cells.

533466

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