Pipelined digital signal processor using a common data and...

G - Physics – 06 – F

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354/230.87

G06F 9/38 (2006.01)

Patent

CA 1165455

Abstract: The present invention relates to a pipelined digital signal processor wherein an ordered stream of data words which are stored in a source is processed through a plurality of processing steps. Each processing step is performed by operation of a separate one of plural processing subsections. Each processing subsection performs under the control of a selected control message (l,m,n) which is included in each control word Ii (l,m,n,s,t) of an ordered stream of control words stored in the source. The separate processing subsections operate concurrently on different data words of the ordered stream of data words. A first message Ii (1) is provided in each control word for controlling a first processing subsection. A second message Ii (m) is provided in each central word for controlling a second processing subsection. A unit is connected to the source for applying the control words to the processing sub- sections, each control word including at least the first and second messages, respectively, for controlling concurrently the first and second processing subsections.

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