Pipelined fft processor with memory address interleaving

Details Pipelined fft processor with memory address interleaving Pipelined fft processor with memory address interleaving

G - Physics

06

F

G06F 17/14 (2006.01) G06F 12/02 (2006.01)

Patent

CA 2451167

A Fast Fourier Transform (FFT) implementation providing a low hardware area butterfly is realized by assuming a one sample per cycle data acquisition rate with minimized adder/multiplier radix-2 butterflies. The use of such butterflies leads to optimization of on-board memory (reduced from 2N-2 to N-1 size) by implementation of a novel address generator which performs a memory interleaving operation through address permutation optimized by reference to known memory requirements.

Affiliated with

Also associated with

Rating

Pipelined fft processor with memory address interleaving does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pipelined fft processor with memory address interleaving, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pipelined fft processor with memory address interleaving will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1772811