Pipelined floating point adder for digital computer

Details Pipelined floating point adder for digital computer Pipelined floating point adder for digital computer

G - Physics

06

F

354/204

G06F 7/50 (2006.01)

Patent

CA 1324217

PIPELINED FLOATING POINT ADDER FOR DIGITAL COMPUTER ABSTRACT A system for subtracting two floating-point binary numbers in a pipelined floating-point adder/subtractor by aligning the two fractions for substraction; arbitrarily designating the fraction of one of the two floating-point numbers as the subtrahend, and producing the complement of that designated fraction; adding that complement to the other fraction, normalizing the result; determining whether the result is negative and, if it is, producing the complement of the normalized result; and selecting the larger of the exponents of the two floating-point numbers, and adjusting the value of the selected exponent in accordance with the normalization of the result. The preferred system produces a sticky bit signal by aligning the two fractions for subtraction by shifting one of the two fractions to the right; determining the number of consecutive zeros in the one fraction, prior to the shifting thereof, beginning at the least significant bit position; comparing (1) the number of positions the one fraction is shifted in the aligning step, with (2) the number of consecutive zeros in the one fraction; and producing a sticky bit signal when the number of consecutive zeros is less than the number of positions the one fraction is shifted in the aligning step, the sticky bit signal indicating the truncation of at least one set bit during the aligning step.

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