Pipelined hardware implementation of a neural network circuit

Details Pipelined hardware implementation of a neural network circuit Pipelined hardware implementation of a neural network circuit

G - Physics

06

N

G06N 3/06 (2006.01) G06F 15/76 (2006.01) G06N 3/063 (2006.01)

Patent

CA 2399250

In a first aspect, a pipelined hardware implementation of a neural network circuit includes an input stage, two or more processing stages and an output stage. Each processing stage includes one or more processing units. Each processing unit includes storage for weighted values, a plurality of multipliers for multiplying input values by weighted values, an adder for adding products outputted from product multipliers, a function circuit for applying a non-linear function to the sum outputted by the adder, and a register for storing the output of the function circuit.

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