Pipelined microprocessor with double bus architecture

Details Pipelined microprocessor with double bus architecture Pipelined microprocessor with double bus architecture

G - Physics

06

F

354/230.87

G06F 9/38 (2006.01) G06F 9/355 (2006.01) G06F 13/00 (2006.01) G11C 7/00 (2006.01)

Patent

CA 1180455

ABSTRACT OF THE DISCLOSURE A two-bus, two instruction type, pipelined microprocessor having a control means which orders appli- cation of instruction and data addresses to a memory and further interleaves instructions and data on a single bus to achieve maximum efficiency in operation.

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