Pipelined phase detector for clock recovery systems

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G01R 25/00 (2006.01) H03L 7/089 (2006.01) H03L 7/091 (2006.01) H04L 7/033 (2006.01)

Patent

CA 2233530

A method of phase detecting a data input NRZ signal comprises applying the input data signal to a pair of parallel channels each comprising the same phase delay, and each clocked using the same clock signal. The phase delayed input data signal is coupled to respective inputs of a pair of phase comparators. The input data signal is coupled to a further channel comprising the same phase delay, and the further channel is clocked using the same clock signal. The phase delayed input signal is passed from the further channel through a further delay which is a fraction of that same phase delay, and the further delay is clocked using the clock signal. The further delayed input data signal is applied to another input of one of the phase comparators. The input data signal is applied through another phase delay which has the fraction of the aforenoted same phase delay (but is unclocked), to another input of the other of the phase comparators. Output signals are obtained from each of the phase comparators.

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