G - Physics – 09 – G
Patent
G - Physics
09
G
G09G 3/32 (2006.01) G09F 9/33 (2006.01)
Patent
CA 2519097
A pixel circuit for use in a display comprising a plurality of pixels is provided. The load-balanced current mirror pixel circuit can compensate for device degradation and/or mismatch, and changing environmental factors like temperature and mechanical strain. The pixel circuit comprises a pixel drive circuit comprising, switching circuitry, a current mirror having a reference transistor and a drive transistor, the reference transistor and the drive transistor each having a first and second node and a gate, the gate of the reference transistor being connected to the gate of the drive transistor; and a capacitor connected between the gate of the reference transistor and a ground potential, and a load connected between the current mirror and a ground potential, the load having a first load element and a second load element, the first load element being connected to the first node of the reference transistor and the second load element being connected to the first node of the drive transistor.
L'invention porte sur un circuit de pixels de commande d'écran à plusieurs pixels comportant un circuit de pixels à miroir de courant et à charges équilibrées compensant la dégradation du dispositif et/ou les défauts de correspondance et les variations des conditions ambiantes telles que la température et les contraintes mécaniques. Le circuit de pixels comporte un circuit de commande de pixels comprenant: un circuit de commutation; un miroir de courant comprenant un transistor de référence et un transistor de commande présentant chacun un premier et un deuxième noeud et une grille, la grille du transistor de référence étant reliée à celle du transistor de commande; un condensateur monté entre la grille du transistor de référence et la terre; et une charge montée entre le miroir de courant et la terre et présentant un premier élément de charge et un deuxième élément de charge, le premier étant relié au premier noeud du transistor de référence, et le deuxième, au premier noeud du transistor de commande.
Jafarabadiashtiani Shahin
Nathan Arokia
Sakariya Kapil
Servati Peyman
Gowling Lafleur Henderson Llp
Ignis Innovation Inc.
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