Pixel matrix with compensation of ohmic drops on the power...

H - Electricity – 04 – N

Patent

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Details

H04N 5/32 (2006.01)

Patent

CA 2701148

A matrix microelectronic device comprising: - a plurality of cells laid out according to a matrix, respectively comprising at least one current source formed by at least one current source transistor (Tl), - a source electrode of said transistor is connected to a source biasing conductor line, - a gate electrode of the transistor (T1) is connected to a gate biasing conductor line (107 1, 107 2) among a plurality of conductor gate biasing lines, wherein the device further comprises means for biasing the conductor gate biasing lines comprising: - at least one first connection line (108, 218), - means for generating current (210) or voltage (110-120), positioned on at least one end of said first connection line, and provided to generate an evolution of potentials along said first connection line.

L'invention concerne un dispositif microélectronique matriciel comprenant une pluralité de cellules disposées en une matrice, qui comprennent chacune au moins une source de courant formée par au moins un transistor de source de courant (T1), une électrode source dudit transistor connectée à une ligne conductrice de polarisation de source, une électrode de grille du transistor (T1) connectée à une ligne conductrice de polarisation de grille (1071, 1072) parmi une pluralité de lignes conductrices de polarisation de grille. Le dispositif comprend, en outre, des moyens de polarisation des lignes conductrice de polarisation de grille, comprenant : au moins une première ligne de connexion (108, 218); des moyens pour générer un courant (210) ou une tension (110-120), positionnés sur au moins une extrémité de ladite première ligne de connexion, et prévus pour générer une évolution de potentiels le long de ladite première ligne de connexion.

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