H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/164
H01L 21/46 (2006.01) H01L 21/312 (2006.01) H01L 21/762 (2006.01)
Patent
CA 1233914
ABSTRACT Disclosed is a process for planarization of semiconductor structures having dielectric isolation regions. Specifically, the process is directed to planarization of an organic polyimide layer obtained following filling of deep trenches in a semiconductor substrate having high and low density trench regions with this material. After over-filling the trenches with the polyimide and obtaining a non-planar poly- imide layer having a thickness much larger in the low trench density regions than that in the high density regions, a photoresist layer is applied thereover. The photoresist is then controllably exposed using a mask which is the complement or inverse of the mask used for imaging the trench patterns to obtain a thick blockout photoresist mask over the trenches and a thin wetting layer of photoresist over the remainder of the substrate. Next, by means of a thermal step, the blockout photoresist is caused to reflow to form a relatively thick photoresist layer over the high trench density regions and a thin photoresist layer over the low trench density regions, thereby exactly compensating for the non-planarity of the polyimide layer.
503286
Cservak Nancy R.
Fribley Susan K.
Goth George R.
Takacs Mark A.
International Business Machines Corporation
Saunders Raymond H.
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