Planarization through silylation

Details Planarization through silylation Planarization through silylation

H - Electricity

01

L

117/23, 204/96.0

H01L 21/312 (2006.01) G03F 7/16 (2006.01) H01L 21/00 (2006.01) H01L 21/3105 (2006.01) H01L 21/768 (2006.01)

Patent

CA 1308609

ABSTRACT OF THE DISCLOSURE Disclosed is a process for forming a planarized multilevel chip wiring structure. Starting from a substrate having thereon at least a metal stud serving as vertical wiring between two levels of metallization, a quartz layer is deposited, obtaining a non-planar structure. A thick planarizing photoactive photoresist is applied. The photoresist is converted by silylation process into a silicate having substantially the same etch rate as that of quartz. Silylation is accomplished by, for example, subjecting the resist to a bath of hexamethyldisilazane, hexamethylcyclotrisilazane, octamethylcyclotetrasilazane, N,N,dimethylaminotrimethylsilane or N,N,diethylaminotrimethylsilane, for a period of time determined by the thickness of the resist. Unwanted portions of the silylated resist and quartz are etched back at 1:1 etch rate ratio to the level of the stud. FI9-86-013

549182

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