Planarizing insulative layers by resputtering

H - Electricity – 01 – L

Patent

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204/96.05

H01L 21/3105 (2006.01)

Patent

CA 1067038

PLANARIZING INSULATIVE LAYERS BY RESPUTTERING ABSTRACT OF THE INVENTION A method of planarizing an electrically insulative layer formed over a non-planar integrated circuit sub- strate having raised portions. After the electrically insulative layers are deposited over such substrate, the layer has elevations corresponding to the underlying raised portions of the substrate. A masking layer is formed on the electrically insulative layer having at least one opening therethrough coincident with an elevation in the insulative layer; this opening has smaller lateral dimensions than the coincident elevation, thereby facilitating alignment. The elevation in the insula- tive layer exposed in said at least one opening is then etched to the level of the unelevated portion of the layer, and the insulative layer is then resputtered for a period of time sufficient to planarize the remainder of such etched elevation to the level of the unelevated portions.

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