Pll and gain control for clock recovery

Details Pll and gain control for clock recovery Pll and gain control for clock recovery

H - Electricity

04

L

H04L 7/033 (2006.01) H03L 7/085 (2006.01) H03L 7/087 (2006.01) H03L 7/093 (2006.01)

Patent

CA 2356242

A high speed data communication system includes a receiver to recover data and clock signals from commu-nicated data. The receiver circuit has a dual phase lock loop (PLL) circuit (200). A fine loop of the PLL includes a phase detector (204) providing a differential analog volt-age output. Transconductance circuitry (210) converts the differential analog voltage output to a low current analog output. The transconductance circuitry has a variable gain which can be controlled by an automatic gain adjust cir-cuit (260, 270). A coarse loop of the PLL allows for fast frequency acquisition of an internal oscillator (212).

Un système de communication de données grande vitesse comporte un récepteur pour récupérer des signaux de données et d'horloge provenant de données communiquées. Le circuit de récepteur comporte un double circuit de boucle à phase asservie (200). Une boucle précise de la boucle à phase asservie comporte un détecteur de phase fournissant un signal de sortie de tension analogique différentiel. Un circuit de transconductance (210) transforme le signal de sortie de tension analogique différentiel en un signal de sortie analogique de courant faible. Le circuit de transconductance présente un gain variable pouvant être commandé par un circuit de réglage automatique de gain (260, 270). Une boucle approximative de la boucle à phase asservie permet de mettre en oeuvre une acquisition de fréquence rapide d'oscillateur interne (212).

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