Pll circuit and method

Details Pll circuit and method Pll circuit and method

H - Electricity

04

L

H04L 7/033 (2006.01) H04N 7/56 (2006.01) H04H 1/00 (2006.01)

Patent

CA 2174197

In order to achieve the above object, a PLL circuit or method for use in a digital broadcasting receiver according to one aspect of the present invention includes; means for or step of receiving a bit stream transmitted from a broadcast station, the bit stream containing a time-signal and a phase-signal, an oscillator for or step of generating system clocks, a counter for or step ofoperating in response to the system clocks from the oscillator, means for applying the bit stream from the receiving means to the oscillator means for or step of controlling the counter so that the counter output matches with the time-signal and the phase-signal, based on differences between both of the time-signal. and the phase-signal through the applying means and the counter output, and load control means for or step of successively loading twice the time-signal and the phrase-signal on the counter in the transmission order of the signals, in the course for looking the frequency and the phase of the system clock provided from the oscillator.

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