Pll circuit and noise reduction means for pll circuit

Details Pll circuit and noise reduction means for pll circuit Pll circuit and noise reduction means for pll circuit

H - Electricity

03

L

H03L 7/18 (2006.01) H03L 7/08 (2006.01)

Patent

CA 2192881

A phase-locked loop frequency synthesizer circuit having reduced phase noise comprises a voltage controlled oscillator for generating and outputting a signal of frequency corresponding to an input control voltage, a frequency divider triggered by either of a rising edge or a falling edge of an output signal of the voltage controlled oscillator for dividing the output signal of the voltage controlled oscillator, a flip-flop triggered by one of the rising edge and the falling edge of the output signal of the voltage controlled oscillator that is not used as a trigger of the frequency divider for taking and outputting the output signal of the frequency divider, a reference clock generator for generating a reference clock of reference frequency, and a phase comparator for outputting a voltage corresponding to a phase difference between an output signal of the flip-flop means and the reference clock.

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