Pll synthesizer and method of controlling the same

Details Pll synthesizer and method of controlling the same Pll synthesizer and method of controlling the same

H - Electricity

03

L

H03L 7/093 (2006.01) H03J 7/06 (2006.01) H03L 7/107 (2006.01) H03L 7/183 (2006.01)

Patent

CA 2139904

The time constant determined by a high-speed time constant circuit (32) is suitable for high-speed pulling of an output frequency (f0), and the time constant determined by the low-speed time constant circuit (33, 34) is suitable for stabilization of the output frequency (f0) at a corresponding value and suppression of a spurious output frequency. When the output frequency (f0) is switched from (f a) to (f b), for example, the output frequency (f0) is switched by setting the frequency division ratio (n) in the state in which the switch (S a) is ON, while the switch (S b) is OFF. Simultaneously, the switch (S a) is turned off, and after the output frequency (f0) is stabilized, the switch (S b) is turned on. The speed of switching the output frequency (f0) is heightened and a spurious output frequency after switching the frequency is suppressed without using an A/D converter or a D/A/ converter having high accuracy.

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