Polishing pad for a semiconductor substrate

Details Polishing pad for a semiconductor substrate Polishing pad for a semiconductor substrate

B - Operations, Transporting

24

B

B24B 37/04 (2006.01) B24D 3/32 (2006.01) B24D 11/00 (2006.01) B24D 13/14 (2006.01) H01L 21/304 (2006.01)

Patent

CA 2336859

A polishing pad for polishing a semiconductor wafer which includes an open- celled porous substrate having sintered particles of synthetic resin. The porous substrate is a uniform, continuous and tortuous interconnected network of capillary passage. The pad includes a bottom surface that is mechanically buffed to improve the adhesion of an adhesive to the pad bottom surface.

L'invention concerne un tampon à polir pour le polissage d'une plaquette en semiconducteur, qui comprend un substrat poreux à structure en alvéoles ouvertes renfermant des particules frittées de résine synthétique. Le substrat poreux se présente sous la forme d'un réseau interconnecté uniforme, continu et tortueux de passages capillaires. Le tampon comporte une surface inférieure brossée mécaniquement, ce qui permet d'améliorer l'adhérence d'un adhésif à ladite surface inférieure.

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