Polishing pads for a semiconductor substrate

Details Polishing pads for a semiconductor substrate Polishing pads for a semiconductor substrate

B - Operations, Transporting

24

B

B24B 37/04 (2006.01) B24B 41/047 (2006.01) B24D 3/32 (2006.01) B24D 13/14 (2006.01)

Patent

CA 2337202

A polishing pad for polishing a semiconductor wafer which includes an open- celled, porous substrate having sintered particles of synthetic resin. The porous substrate is a uniform, continuous and tortuous interconnected network of capillary passage. The pores of the porous substrate have an average pore diameter of from about 5 to about 100 microns which enhances pad polishing performance.

L'invention concerne un tampon à polir pour le polissage d'une plaquette en semiconducteur, qui comprend un substrat poreux à structure en alvéoles ouvertes renfermant des particules frittées de résine synthétique. Le substrat poreux se présente sous la forme d'un réseau interconnecté uniforme, continu et tortueux de passages capillaires. Les pores du substrat poreux ont un diamètre moyen compris entre environ 5 et environ 100 microns, ce qui permet d'améliorer les performances de polissage.

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