Power and bit loading allocation in a communication system...

H - Electricity – 04 – L

Patent

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Details

H04L 27/26 (2006.01) H04B 7/005 (2006.01) H04B 7/06 (2006.01) H04L 1/00 (2006.01)

Patent

CA 2497392

The present invention is concerned with optimising bit loading and power allocation in a communication system for transferring data between a transmitter and a receiver over a plurality of channels. The system comprises modulation circuitry having a plurality of different modulation alphabets thereby providing a set of possible bit loading sequences. The system also has circuitry for determining the power to be allocated for each bit loading sequence based on minimising the error rate and circuitry for selecting the bit loading sequence with the lowest bit error rate.

L'invention porte sur l'optimisation du chargement binaire et de l'affectation de puissance dans un système de communication conçu pour transférer des données entre un émetteur et un récepteur sur une pluralité de canaux. Le système comprend des circuits de modulation ayant une pluralité de divers alphabets de modulation, ce qui permet de fournir un ensemble de possibilités de séquences de chargement binaire. Le système comprend également des circuits conçus pour déterminer la puissance à affecter à chaque séquence de chargement binaire sur la base de la minimisation du taux d'erreurs, et des circuits permettant de sélectionner la séquence de chargement binaire à plus bas taux d'erreurs binaires.

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