Power detecting circuit and demodulator comprising it

H - Electricity – 03 – D

Patent

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H03D 1/18 (2006.01)

Patent

CA 2465128

A power detecting circuit and a demodulating circuit comprising it in which two transistors (FET) Q101, Q102 of substantially the same characteristics connected with a resistor element R103 as a current source at the joint of sources are employed as active elements, substantially equal bias voltages are fed to the gate and drain of the transistors Q101, Q102, a capacitor C104 set with a sufficiently high capacitance is connected between the sources of the transistors Q101, Q102 and the earth, capacitors C102, C103 set with a substantially equal and sufficiently high capacitance are connected between the drains of the transistors Q101, Q102 and the earth, a high frequency signal Rfin is fed to the gate of the transistor Q101 and the voltage difference between the drains of the transistors Q101, Q102 is detected as a detection output.

L'invention concerne un circuit de détection de puissance et un circuit de démodulation comprenant ledit circuit de détection de puissance. Ce circuit de détection de puissance comprend deux transistors (FET) Q101 et Q102, possédant sensiblement les mêmes caractéristiques, connectés à un élément de résistance R103 comme source de courant au niveau de la liaison des sources, utilisés comme éléments actifs de tensions de polarisation sensiblement égales alimentant la grille et le drain des transistors Q101 et Q102; un condensateur C104 réglé à une capacitance suffisamment élevée connecté entre les sources des transistors Q101 et Q102 et la terre; des condensateurs C102, C103 réglés à une capacitance sensiblement égale et suffisamment élevée connectés entre les drains des transistors Q101 et Q102 et la terre; et un signal à fréquence élevée Rfin fourni à la grille du transistor Q101, la différence de tension entre les drains des transistors Q101 et Q102 étant détectée sous forme d'une sortie de détection.

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