Power semiconductor packaging method and structure

Details Power semiconductor packaging method and structure Power semiconductor packaging method and structure

H - Electricity

01

L

H01L 23/02 (2006.01) H01L 21/70 (2006.01) H01L 21/768 (2006.01) H01L 23/055 (2006.01) H01L 23/48 (2006.01)

Patent

CA 2555394

A semiconductor chip packaging structure comprising a dielectric film 10 having one or more through holes 11 aligned with the one or more contact pads 22 and 23 of at least one power semiconductor chip 21. A patterned electrically conductive layer 40 adjacent to the dielectric film 10 has one or more electrically conductive posts 41 which extend through the one or more though holes 11 aligned with the contact pads 22 and 23 to electrically couple the conductive layer 40 to the contact pads 22 and 23. In certain embodiments, one or more air gaps 91 may be formed between the dielectric film 10 and the active surface 24 of the at least one power semiconductor chip 21. Methods for fabricating the semiconductor chip packaging structure are also disclosed.

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