H - Electricity – 04 – B
Patent
H - Electricity
04
B
325/15
H04B 1/40 (2006.01) H02M 3/07 (2006.01)
Patent
CA 1260543
ABSTRACT A power switch circuit which is compact and has a mini- mized current consumption is disclosed. The circuit is designed such that load breakdown and/or degradation of performance thereof is prevented even when the power source is connected to the load with terminals reversed. The power switch circuit includes a power source for providing a direct current (DC) voltage, a voltage booster circuit for boosting the DC voltage and a switch connected between the power source and the voltage booster circuit for on-off controlling the voltage booster circuit. A first enhancement mode MOS FET having the drain or source connected to the power source and the gate connected to the output of the vol- tage booster circuit is also included as well as a second enhance- ment mode MOS FET having the source or drain connected to the source or drain of the first enhancement MOS FET and the gate connected to the output of the voltage booster circuit. The source or drain of the second enhancement mode MOS FET is connectible to a load.
524885
Fukumura Yukio
Ikeda Shigeki
Corporation Nec
Smart & Biggar
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