Power-up detector for low power systems

Details Power-up detector for low power systems Power-up detector for low power systems

H - Electricity

03

L

H03L 7/00 (2006.01) H03K 17/22 (2006.01)

Patent

CA 2260867

A power-up reset detector circuit is described which uses the threshold voltages of NMOS and PMOS transistors (M7 and M8) to detect the power-up of integrated circuits, and uses a current mirror (M2 through M6) to track power supply and process variations.

Cette invention concerne un circuit de détection de la mise sous tension qui utilise les tensions de seuil de transistors NMOS et PMOS pour détecter la mise sous tension de circuits intégrés, et utilise un miroir de courant pour détecter l'alimentation en énergie et traiter les variations.

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