H - Electricity – 03 – K
Patent
H - Electricity
03
K
328/115
H03K 3/38 (2006.01) H03K 17/92 (2006.01) H03K 19/195 (2006.01)
Patent
CA 1078464
A POWERING SCHEME FOR JOSEPHSON LOGIC CIRCUITS WHICH ELIMINATES DISTURB SIGNALS Abstract of the Disclosure A Josephson junction terminated line logic powering scheme is disclosed wherein a logic gate and a regulating gate are utilized in at least a single logic circuit to provide a constant voltage to the logic circuit. The circuit comprises a terminated line logic gate with its associated sense gate and a regulating gate in series with the logic gate. When the logic gate is switched to the voltage state, it sends a disturb signal up and down the line which carries the gate current to the logic devices. A regulator gate which has already been biased to the voltage state is reset to the zero voltage state by the disturb signal. The resetting of the regulator gate sends out a disturb signal which cancels the original disturb signal with a small delay. The result of the combination of the disturbance generated by the logic gate and the regulating gate is an extremely narrow pulse with a maxi- mum width equal to the round trip delay between the adjacent gates having an amplitude of 1-1min. In the steady state, the total voltage drop across the supply line remains constant before and after logic opera- tions. Thus, d.c. regulation problems are eliminated. Using this approach for powering logic gates, it is possible to reset the logic gates by applying a control pulse to the regulating gates so that all of these gates which are in the zero voltage state will be switched to the voltage state. The disturbance resulting from this switching action resets the adjacent logic gate in the same manner as the logic. -1-
249269
Fang Frank F.
Herrell Dennis J.
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