Pre-execution next address calculating mechanism

Details Pre-execution next address calculating mechanism Pre-execution next address calculating mechanism

G - Physics

06

F

354/230.81

G06F 9/40 (2006.01) G06F 9/32 (2006.01) G06F 9/38 (2006.01)

Patent

CA 1193738

PRE-EXECUTION NEXT ADDRESS CALCULATING MECHANISM Abstract Two consecutive instructions are transferred from the main memory of a computer to an instruction fetch unit. Each instruction comprises an op code, an operand, and an address field for indicating the address of the next instruction. The two instructions comprise the current instruction and the next sequential instruction, when the next sequential instruction is a branch instruction, the branch is eliminated by including the target of the branch in a next address field which is made a part of the previous instruction. By this method, the need to execute separate branch instructions is substantially eliminated.

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