Precision resistor in self-aligned silicided mos process

Details Precision resistor in self-aligned silicided mos process Precision resistor in self-aligned silicided mos process

H - Electricity

01

L

H01L 27/088 (2006.01) H01L 21/329 (2006.01) H01L 21/8238 (2006.01) H01L 27/04 (2006.01) H01L 27/06 (2006.01)

Patent

CA 2041362

A precision resistor is formed in an integrated circuit by a diffused region created at the same time as transistor source/drain regions. In a CMOS process, this N-type resistor region is formed in an N-well, as is used for P-channel transistors. The resistor formed using a deposited oxide layer as a mask, and this oxide layer is also used to create sidewall spacers for the transistor gates. The sidewall spacers are used in creating self-aligned silicided areas over the source/drain regions, self-aligned with the gates, and the silicide is also used for contact areas for the resistor. The value of the resistor is defined by the width of the deposited oxide layer left as a mask, but this does not require any critical alignment steps.

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