Predictive clock recovery circuit

Details Predictive clock recovery circuit Predictive clock recovery circuit

H - Electricity

04

L

328/87

H04L 7/02 (2006.01) H04L 7/033 (2006.01)

Patent

CA 1286000

ABSTRACT Predictive clock extracting circuit which having means for determining the duration between two consecutive transitions of a multilevel digital signal, and means for generating a pulse SPL at half the said duration after a the transition following on two consecutive previous transitions. A phase locked oscillator driven by said SPL pulse generates the extracted clock signal, in phase with pulse SPL and which coincides with the center of the eye intervals of said multilevel digital signal. The system includes a first counter N which starts running in response to the detection of the first transition of the multilevel digital signal. The running stops when the second transition occurs, the result N(i) stored into the first counter N at second transition is therefore representative of the duration between the two consecutive first and second transitions. A divide by 2 circuit divides the result N(i) stored into the first counter at second transition. The preferred embodiment of the invention also involves an an up/down counter which generates a second counter K that is expected to be representative of half the value of the first counter N(i). This second counter K is used to generate the extracted clock in phase with the middle of the eye intervals. Counter K is adaptively updated by incrementing its current value K(i) by a fixed factor or, on the contrary, by decrementing its current value K(i) by a fixed damping factor. A comparator comparing K(i) and N(i)/2 controls the update of the current value K(i) according the following rules. if the value K(i) is superior to N(i)/2 at the second transition, then the counter K is updated by decrementing its current value. Conversely, when N(i) is inferior to N(i)/2, then counter K is updated by incrementing its current value. In this way, the extracted clock which will be derived from counter K varies slowly and integrates sudden variations of the content of the first counter N. A counter P initialized with the updated value K(i+l) of counter K starts running from K(i+l) to zero in response to the detection of the transition following on two said first and second transition and delivers a pulse SPL whenever its content reaches the value zero. The phase locked oscillator controlled by the pulse SPL generates the extracted clock which is likely to coincide with the middle of the eye pattern.

576316

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