Preprocessing implied specifiers in a pipelined processor

Details Preprocessing implied specifiers in a pipelined processor Preprocessing implied specifiers in a pipelined processor

G - Physics

06

F

354/230.72

G06F 9/38 (2006.01) G06F 9/30 (2006.01) G06F 9/318 (2006.01)

Patent

CA 1323940

PREPROCESSING IMPLIED SPECIFIERS IN A PIPELINED PROCESSOR ABSTRACT An instruction decoder generates implied specifiers for certain predefined instructions, and an operand processing unit preprocess most of the implied specifiers in the same fashion as express operand specifiers. For instructions having an implied autoincrement or autodecrement of the stack pointer, an implied read or write access type is assigned to the instruction and the decode logic is configured accordingly. When an opcode is decoded and is found to have an implied write specifier, a destination operand is created for autodecrementing the stack pointer. If an opcode is decoded and found to have an implied read specifier, a source operand is created for autoincrementing the stack pointer. A register or short literal specifier can be decoded simultaneously with the generation of the implied operand. Therefore some common instructions such as "PUSH Rx" can be decoded in a single cycle. The preprocessing of implied specifiers in addition permits more complex instructions such as "BSR DEST" to be executed in a single cycle. Conflicts created by the implied specifiers are handled in the same manner as conflicts for express specifiers. Moreover, by using the same data paths for both the implied specifiers and the express specifiers, and by inserting queues between the instruction unit and the execution unit, performance gains are realized for instructions having implied specifiers as well as just express specifiers.

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