Priority interrupt logic circuits

Details Priority interrupt logic circuits Priority interrupt logic circuits

G - Physics

06

F

354/230.85

G06F 9/46 (2006.01) G06F 13/26 (2006.01)

Patent

CA 1095628

ABSTRACT OF THE DISCLOSURE Priority interrupt apparatus includes a level priority network, a plurality of priority networks, and selector cir- cuits, each corresponding in number to the number of channel sources operative to generate interrupt requests. Each pri- ority network receives request signals corresponding to dif- ferent types of possible event signals requiring attention and produces a type code designating the highest priority event from the channel associated therewith. The priority is established in accordance with a preassigned event pri- ority approximating the priorities assignable by program. Each of the selector circuits is connected to receive as a control input the type code signals generated by the pri- ority network associated therewith. Additionally, each selector circuit receives a different set of interrupt level number signals representative of priorities assigned by pro- gram to the number of possible event signals. In response to the request signals, the selector circuit of each channel source applies as an input to the level priority network the programmed designated set of interrupt level number signals specified by the type code signals. The level priority net- work includes a number of compare circuits and output gating circuits. Each compare circuits provides signal indications as to which one of a pair of channels has the higher priority -1- event as defined by the selected interrupt level signals. Signals indicating the results from each compare circuits are then applied to the output gating circuits which gener- ate a code for selecting the type code and interrupt level signals of the channel source receiving the highest priority event. -2-

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