Private cache to cpu interface in a bus oriented system

Details Private cache to cpu interface in a bus oriented system Private cache to cpu interface in a bus oriented system

G - Physics

11

C

354/237

G11C 7/00 (2006.01) G06F 12/08 (2006.01)

Patent

CA 1126871

ABSTRACT In a data processing system which includes a plurality of system units all connected in common to a system bus and communicating with each other via the system bus, a private (Central Processor Unit) CPU - Cache Memory Interface for permitting direct cache memory read access by the CPU, and allowing the full monitoring of main memory write operations via the system bus between the CPU and main memory. The cache-to-processor private interface is used only for selected memory read accesses; thus the system bus interface remains available for other CPU to system bus operations, min- imizing information traffic congestion on the system bus.

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